SELSE 2008 - Call for Participation

Advance Registration Deadline : March 14, 2008!

CALL FOR PARTICIPATION

Overview

The growing complexity and shrinking geometries of modern device technologies are making high-density, low-voltage devices increasingly susceptible to influences from electrical noise, process variation, and natural radiation interference. System-level effects of these errors can be far reaching. Growing concerns about intermittent errors, erratic storage cells, and the effects of aging are influencing system design. This workshop provides a forum for discussing current research and practices in system-level error management. Participants from industry and academia explore both current technologies and future research direction (including nanotechnology). Papers cover system-level effects of errors from a variety of perspectives: architectural, logical and circuit-level, and semiconductor processes.

Key topics include:

Technology trends and the impact on error rates
New error mitigation techniques
Characterization of the overhead and design complexity of error mitigation techniques
Case studies describing the engineering tradeoffs necessary to decide what mitigation techniques to apply
Experimental data
System-level models: derating factors and validation of error models
Error handling protocols (higher-level protocols for robust system design

Registration

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For more information on registration please visit the online registration.

Committees

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Workshop Co-chairs
Wendy Bartlett, HP
Babak Falsafi, Carnegie Mellon / EPFL

Program Co-chairs
Dennis Abts, Google
Alan Wood, Sun

Publications Chair
Norbert Seifert, Intel

Local Arrangements Chair
Michael Orshansky, University of Texas, Austin

Publicity Chair
Vivian Zhu, TI

Steering Committee
Wendy Bartlett (Hewlett-Packard)
Subhasish Mitra (Stanford University)
Pia Sanda (IBM)

Organizing Committee
Dennis Abts (Google)
Wendy Bartlett (Hewlett-Packard)
Babak Falsafi (Carnegie-Mellon, EPFL)
Jeff Kellington (IBM)
Sarah Michalak (Los Alamos Natl Lab)
Michael Orshansky (University of Texas, Austin)
Sanjay Patel (University of Illinois, Urbana-Champaign)
Norbert Seifert (Intel)
Jeff Wilkinson (Medtronic)
Alan Wood (Sun)
Vivian Zhu (Texas Instruments)

Advisory Committee
Sarita Adve (University of Illinois)
Ravi Iyer (University of Illinois)
Nur Touba (University of Texas)

For more information, visit us on the web at: http://www.selse.org

The 4th IEEE International Workshop on Silicon Errors in Logic - System Effects (SELSE 2008) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC)

Advance Registration Deadline : March 14, 2008!
CALL FOR PARTICIPATION
Overview -- Registration -- Committees
Overview
The growing complexity and shrinking geometries of modern device technologies are making high-density, low-voltage devices increasingly susceptible to influences from electrical noise, process variation, and natural radiation interference. System-level effects of these errors can be far reaching. Growing concerns about intermittent errors, erratic storage cells, and the effects of aging are influencing system design. This workshop provides a forum for discussing current research and practices in system-level error management. Participants from industry and academia explore both current technologies and future research direction (including nanotechnology). Papers cover system-level effects of errors from a variety of perspectives: architectural, logical and circuit-level, and semiconductor processes. Key topics include: Technology trends and the impact on error rates New error mitigation techniques Characterization of the overhead and design complexity of error mitigation techniques Case studies describing the engineering tradeoffs necessary to decide what mitigation techniques to apply Experimental data System-level models: derating factors and validation of error models Error handling protocols (higher-level protocols for robust system design
Registration	top
For more information on registration please visit the online registration.
Committees	top
Workshop Co-chairs Wendy Bartlett, HP Babak Falsafi, Carnegie Mellon / EPFL Program Co-chairs Dennis Abts, Google Alan Wood, Sun Publications Chair Norbert Seifert, Intel Local Arrangements Chair Michael Orshansky, University of Texas, Austin Publicity Chair Vivian Zhu, TI Steering Committee Wendy Bartlett (Hewlett-Packard) Subhasish Mitra (Stanford University) Pia Sanda (IBM) Organizing Committee Dennis Abts (Google) Wendy Bartlett (Hewlett-Packard) Babak Falsafi (Carnegie-Mellon, EPFL) Jeff Kellington (IBM) Sarah Michalak (Los Alamos Natl Lab) Michael Orshansky (University of Texas, Austin) Sanjay Patel (University of Illinois, Urbana-Champaign) Norbert Seifert (Intel) Jeff Wilkinson (Medtronic) Alan Wood (Sun) Vivian Zhu (Texas Instruments) Advisory Committee Sarita Adve (University of Illinois) Ravi Iyer (University of Illinois) Nur Touba (University of Texas)
For more information, visit us on the web at: http://www.selse.org
The 4th IEEE International Workshop on Silicon Errors in Logic - System Effects (SELSE 2008) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC)